Typically, CPU chipsets are not normally considered systems-on-chip (SoC) but the fourth generation of AMD EPYC processors incorporate numerous I/O functionality at a high level of integration. Previous generations have delivered this functionality on external chipsets. The SoC design helps reduce power consumption, packaging costs and improve data throughput by reducing interconnection latencies.
The new EPYC processors have 12 DDR5 memory controllers – 50 percent more controllers than any other x86 CPU, which keeps up the higher memory demands of performance-intensive computing applications. As we mentioned in an earlier blog, these controllers also include inline encryption engines for supporting AMD’s Infinity Guard features, including support for an integrated security processor that establishes a secure root of trust and other security tasks.
They also include 128 or 160 lanes of PCIe Gen5 controllers, which also helps with higher I/O throughput of these more demanding applications. These support the same physical interfaces for Infinity fabric connectors and provide more remote memory access among CPUs at up to 36 GBps between servers. The new Zen 4 CPU cores can make use of one or two interfaces.
The PCIe Gen 5 I/O is supported in the I/O die with eight serializer/deserializer silicon controllers with one independent set of traces to support each port of 16 PCIe lanes.
